Clock signal generator/converter device

ABSTRACT

The device converts a clock signal into a second clock signal having a different clock rate. This allows converting a first data signal into a second data signal having an altered data rate. Controlling the frequency dividers particularly in the feedback path of the phase-locked loops enables matching to the different data rates and conversion between both data signals DS 1  into DS 2 , or DS 2  into DS 1.

BACKGROUND OF THE INVENTION Field of the Invention

[0001] The invention relates to a clock signal generator/converterdevice with the aid of which a first data signal is converted into asecond data signal having a different data rate.

[0002] For data transmission protected by error correction, the datarate can be increased. At the receiving end, the original data signalcan be recovered from the transmitted signal.

[0003] Thus, for example for the transmission of SDH signals(synchronous digital hierarchy) via submarine cables according to ITU-G.975, it has recommended to introduce an error correction, for whichpurpose the transmission rate is increased to 15/14 of the original datarate. The use of the corresponding devices will be explained withreference to FIG. 1. From a subscriber, a first data signal istransmitted in a first access network AN1. As early as here it may benecessary to use a first regenerator R1. The latter forwards aregenerated data signal which is transmitted in an optical network ON ina manner protected with the aid of correction bits. In the converterterminal TT, firstly an assigned clock signal is obtained from the datasignal DS and the clock signal is converted into a clock signal having ahigher data rate, which corresponds to the transmission rate of a seconddata signal DS2 having correction bits. A further regenerator R2 may benecessary for amplitude, pulse-shape and clock regeneration in theoptical network. In the reconverter terminal TR, firstly an assignedsecond clock signal is obtained from the data signal DS2 and convertedinto a first clock signal TS1, which is again assigned to the recoveredfirst data signal DS1.

SUMMARY OF THE INVENTION

[0004] The object of the invention is to provide a suitable clock signalgenerator/converter device, in particular for the transmission terminaland the reception terminal, which overcomes the above-noted deficienciesand disadvantages of the prior art devices and methods of this generalkind. The device is also intended to be useable in the regenerators.

[0005] With the above and other objects in view there is provided, inaccordance with the invention, a clock signal generator/converterdevice, comprising:

[0006] a first phase-locked loop for obtaining a first clock signal froma respective one of a plurality of data signals having mutuallydifferent data rates, the first phase-locked loop receiving a respectivedata signal as a reference signal;

[0007] the first phase-locked loop having a feedback path with a firstadjustable frequency divider for coarse matching to the different datarates;

[0008] a frequency divider connected to receive the first clock signal;

[0009] a second phase-locked loop connected to receive the first clocksignal as a second reference signal via the frequency divider, thesecond phase-locked loop converting the first clock signal into anassigned second clock signal having a different clock frequency;

[0010] the second phase-locked loop having a feedback path with a secondadjustable frequency divider for coarse matching to the different datarates of the data signals and with a third frequency divider forgenerating the second clock signal having the different clock frequency.

[0011] The possibility of changeover means that the novel device can beused universally. This is the essential advantage of the device.Additional advantages and features are found in the following summary.

[0012] In accordance with an added feature of the invention, a thirdfrequency divider is connected in the feedback path of the secondphase-locked loop, and the third frequency divider and the frequencydivider connected between the first and second phase-locked loops areadjustable to selectively set an increase and a reduction in the clockrate of the second clock signal relative to a clock rate of the firstclock signal.

[0013] In accordance with an additional feature of the invention, afurther frequency divider having a fractional rational division ratio isconnected in the feedback path of the second phase-locked loop.

[0014] In accordance with another feature of the invention, the divisionratio of the further frequency divider is adjustable for selectivelysetting an increase and a reduction in the clock frequency of the secondclock signal relative to a clock frequency of the first clock signal.

[0015] In accordance with a further feature of the invention, thefurther frequency divider is a fifth frequency divider, and a sixthfrequency divider is connected downstream of the fifth frequency dividerin a signal flow direction.

[0016] In accordance with again an added feature of the invention, thefrequency divider in the feedback path of the second phase-locked loopis additionally adjustable to set the clock frequency of the first clocksignal identical to the clock frequency of the second clock signal.

[0017] In accordance with again an additional feature of the invention,a controller is connected to and configured to adjust the frequencydividers, the controller containing information concerning the data rateof the first data signal/the clock rate of the first clock signal andthe data rate of the second data signal/the clock rate of the secondclock signal.

[0018] In accordance with again another feature of the invention, thedata rate of the first data signal is determined by a frequencydiscriminator of the first phase-locked loop and a controller, and thefirst frequency divider of the first phase-locked loop is adjustedaccordingly, and wherein the second phase-locked loop is adjusted on abasis of additional information, which may be stored or transmitted.

[0019] In accordance with a concomitant feature of the invention, thereare provided identical controllable oscillators in the first and secondphase-locked loops.

[0020] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0021] Although the invention is illustrated and described herein asembodied in a clock signal generator/converter device, it isnevertheless not intended to be limited to the details shown, sincevarious modifications and structural changes may be made therein withoutdeparting from the spirit of the invention and within the scope andrange of equivalents of the claims.

[0022] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a diagram of an application of the invention;

[0024]FIG. 2 is a schematic block diagram of a first exemplaryembodiment of the invention; and

[0025]FIG. 3 is a schematic block diagram of a second exemplaryembodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The device according to the invention is intended to be used, asalready explained in the above introductory text in the description withreference to FIG. 1, in particular at the interfaces between unprotectedoptical networks AN1, AN2 and an optical network ON which is protectedby error correction (and can be monitored in synchronous digitalhierarchy, SDH, networks by means of an OH byte.

[0027] Referring now to the figures of the drawing showing the noveldevice in detail and first, particularly, to FIG. 2 thereof, there isseen a clock signal generator/converter device according to theinvention. It essentially contains two phase-locked loops PLL1 and PLL2and also a controller ST1. The first phase-locked loop PLL1 contains aphase/frequency discriminator PD/FD1, a filter FI1, a first controllableoscillator VCO1 and, in the feedback circuit, an adjustable firstfrequency divider FT1. A first data signal DS1 is fed as referencesignal f_(R1) to the phase/frequency discriminator PD/FD1 via an input.Moreover, the discriminator can be tuned by a frequency adjusting signalFE. The first frequency divider FT1 is adjusted in accordance with thedata rate of the data signal DS1 by means of a data rate control signalDRS from the controller ST1, which receives control information STI fromthe network management. This frequency divider enables the circuit to beused at a wide variety of data rates. By virtue of the phase/frequencydiscriminator PD/FD1, reliable lock-on of the first phase-locked loopPLL1 is achieved and the first clock signal TS1 is generated. With thelatter, the data signal DS1 is buffer-stored in a sampling flip-flopFF1.

[0028] The second phase-locked loop PLL2 receives the first clock signalTS1 or a signal derived therefrom by frequency division as secondreference signal f_(R2). This second phase-locked loop PLL2 is intendedfirstly to supply a somewhat increased data rate. For this purpose, asecond frequency divider FT2 and a third frequency divider FT3 arearranged in the feedback circuit. The second frequency divider FT2 hasthe same division ratio as the first frequency divider FT1 and isadjusted together with the latter in accordance with the data rate ofthe data signal DS1 present. The third frequency divider FT3 has adivision ratio of m:1, while the frequency divider FT4 which isconnected upstream of the second phase/frequency discriminator PD/FD2has a division ratio of n:1. Consequently, in accordance with thedivision ratio m:n, in this case 15:14, a second clock signal TS2 havingan increased clock rate is generated. With this clock signal, thebuffer-stored data of the first data signal DS1 and additionalcorrection bits FEC are combined by means of a multiplexer and outputvia a transmission flip-flop FF2 as second data signal DS2. If the thirdfrequency divider FT3 and the frequency divider FT4 connected upstreamare made adjustable, then the clock frequency of the second clock signalTS2 can remain identical or be increased or decreased relative to thefirst clock frequency TS1. In the application specified, the same devicecan be utilized for converting a second data signal DS2 in a receptionterminal TR (FIG. 1) into a first data signal DS1 (a buffer store thatis required is not illustrated). For this purpose, it is necessarymerely to interchange the division ratios of the frequency dividers FT3and FT4. If both division ratios are identical, the device can be usedas a regenerator.

[0029] Referring now to FIG. 3, there is illustrated a variant of thesecond phase-locked loop. Here, the recovery is effected with the aid ofa fifth frequency divider FT5, which has a fractional rational divisionratio m:n or n:m. This frequency divider is connected together with asixth frequency divider FT6 into the feedback path of the phase-lockedloop. The sixth frequency divider has a division ratio of (N×K):1 andcan be adjusted by the mode control signal MS. The second referencesignal f_(R2) is obtained by means of a frequency divider FT7 connectedupstream and having the division ratio K:1. The frequency divider FT6 isexpedient for compensating the sudden phase changes caused by thefractional rational frequency divider FT5. Depending on the divisionratios m:n and N:1, it may be possible to dispense with frequencydivision by the factor K and thus also with the frequency divider FT7connected upstream. The second clock signal is obtained once again withthe aid of the frequency divider FT2.

[0030] A variant ST2 of the controller is provided here which has noinformation about the data rate of the received data signal. This isdetermined by the phase/frequency discriminator with the aid of anexternal reference signal VS. The further adjustment is effected in themanner already described, depending on whether the data rate is intendedto be increased or decreased.

I claim:
 1. A clock signal generator/converter device, comprising: afirst phase-locked loop for obtaining a first clock signal from arespective one of a plurality of data signals having mutually differentdata rates, said first phase-locked loop receiving a respective datasignal as a reference signal; said first phase-locked loop having afeedback path with a first adjustable frequency divider for coarsematching to the different data rates; a frequency divider connected toreceive the first clock signal; a second phase-locked loop connected toreceive the first clock signal as a second reference signal via saidfrequency divider, said second phase-locked loop converting the firstclock signal into an assigned second clock signal having a differentclock frequency; said second phase-locked loop having a feedback pathwith a second adjustable frequency divider for coarse matching to thedifferent data rates of the data signals and with a third frequencydivider for generating the second clock signal having the differentclock frequency.
 2. The device according to claim 1, which comprises athird frequency divider connected in said feedback path of said secondphase-locked loop, and wherein said third frequency divider and saidfrequency divider connected between said first and second phase-lockedloops are adjustable to selectively set an increase and a reduction inthe clock rate of the second clock signal relative to a clock rate ofthe first clock signal.
 3. The device according to claim 1, whichcomprises a further frequency divider having a fractional rationaldivision ratio connected in said feedback path of said secondphase-locked loop.
 4. The device according to claim 3, wherein thedivision ratio of said further frequency divider is adjustable forselectively setting an increase and a reduction in the clock frequencyof the second clock signal relative to a clock frequency of the firstclock signal.
 5. The device according to claim 4, wherein said furtherfrequency divider is a fifth frequency divider, and a sixth frequencydivider is connected downstream of said fifth frequency divider in asignal flow direction.
 6. The device according to claim 3, wherein saidfurther frequency divider is a fifth frequency divider, and a sixthfrequency divider is connected downstream of said fifth frequencydivider in a signal flow direction.
 7. The device according to claim 5,wherein said frequency divider in said feedback path of said secondphase-locked loop is additionally adjustable to set the clock frequencyof the first clock signal identical to the clock frequency of the secondclock signal.
 8. The device according to claim 2, wherein said frequencydivider in said feedback path of said second phase-locked loop isadditionally adjustable to set the clock frequency of the first clocksignal identical to the clock frequency of the second clock signal. 9.The device according to claim 7, which comprises a controller connectedto and configured to adjust said frequency dividers, said controllercontaining information concerning the data rate of the first datasignal/the clock rate of the first clock signal and the data rate of thesecond data signal/the clock rate of the second clock signal.
 10. Thedevice according to claim 1, which comprises a controller connected toand configured to adjust said frequency dividers, said controllercontaining information concerning the data rate of the first datasignal/the clock rate of the first clock signal and the data rate of thesecond data signal/the clock rate of the second clock signal.
 11. Thedevice according to claim 1, wherein the data rate of the first datasignal is determined by a frequency discriminator of said firstphase-locked loop and a controller, and said first frequency divider ofsaid first phase-locked loop is adjusted accordingly, and wherein saidsecond phase-locked loop is adjusted on a basis of additionalinformation.
 12. The device according to claim 11, wherein theadditional information is stored or transmitted.
 13. The deviceaccording to claim 1, which comprises identical controllable oscillatorsin said first and second phase-locked loops.